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[Develop Tools复件 数字锁相环程序

Description: 数字锁相环DPLL源程序,用cpld编写,展开后文件比较多,大家请耐心使用。谢谢,多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: | Size: 121143 | Author: zhangfj_99 | Hits:

[Other resourcechip1

Description: CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
Platform: | Size: 30562 | Author: sss | Hits:

[Other resourcedpll0226

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 184894 | Author: sss | Hits:

[Other resourceDPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 279141 | Author: sss | Hits:

[Other resourcepll1218

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 109264 | Author: sss | Hits:

[Develop Toolschangyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793855 | Author: 1 | Hits:

[matlabDPLL

Description: 数字锁相环DPLL实例程序,帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
Platform: | Size: 1024 | Author: 李向坤 | Hits:

[Books复件 数字锁相环程序

Description: 数字锁相环DPLL源程序,用cpld编写,展开后文件比较多,大家请耐心使用。谢谢,多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Platform: | Size: 120832 | Author: | Hits:

[VHDL-FPGA-Verilogdpll0227

Description: DPLL同步提取有一定效果-DPLL simultaneously extract a certain effect 11111111111111111111111
Platform: | Size: 272384 | Author: s | Hits:

[VHDL-FPGA-Verilogchip1

Description: CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
Platform: | Size: 30720 | Author: sss | Hits:

[VHDL-FPGA-Verilogdpll0226

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 184320 | Author: sss | Hits:

[VHDL-FPGA-VerilogDPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 278528 | Author: sss | Hits:

[VHDL-FPGA-Verilogpll1218

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 108544 | Author: sss | Hits:

[Bookschangyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793600 | Author: 1 | Hits:

[VHDL-FPGA-VerilogDPLL

Description: 90度锁定的数字锁相环的设计的VHDL源代码-The VHDL code of Digital Phase-Locked Loop Based on CPLD
Platform: | Size: 350208 | Author: sunjinqiu | Hits:

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